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Probabilistic computing is a computing scheme that offers a more efficient approach than conventional complementary metal-oxide–semiconductor (CMOS)-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic magnetic tunnel junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, by combining stochastic MTJs with 2D-MoS₂field-effect transistors (FETs), we demonstrate an on-chip realization of a p-bit building block displaying voltage-controllable stochasticity. Supported by circuit simulations, we analyze the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. While the current approach has not reached the level of maturity required to compete with CMOS-compatible MTJ technology, the design rules presented in this work are valuable for future experimental implementations of scaled on-chip p-bit networks with reduced footprint. 

Contact engineering on monolayer layer (ML) semiconducting transition metal dichalcogenides (TMDs) is considered the most challenging problem towards using these materials as a transistor channel in future advanced technology nodes. The typically observed strong Femi level pinning induced in part by the reaction of the source/drain contact metal and the ML TMD frequently results in a large Schottky barrier height, which limits the electrical performance of ML TMD field-effect transistors (FETs). However, at a microscopic level, little is known about how interface defects or reaction sites impact the electrical performance of ML TMD FETs. In this work, we have performed statistically meaningful electrical measurements on at least 120 FETs combined with careful surface analysis to unveil contact resistance dependencies on the interface chemistry. In particular, we achieved a low contact resistance for ML MoS2 FETs with ultra-high vacuum (UHV, 3×10-11 mbar) deposited Ni contacts, ~500 ohm·μm, which is 5 times lower than the contact resistance achieved when deposited at high vacuum (HV, 3×10-6 mbar) conditions. These electrical results strongly correlate with our surface analysis observations. X-ray photoelectron spectroscopy (XPS) revealed significant bonding species between Ni and MoS2 under UHV conditions compared to HV. We also studied the Bi/MoS2 interface under UHV and HV deposition conditions. Different from the case of Ni, we do not observe a difference in contact resistance or interface chemistry between contacts deposited under UHV and HV. Finally, this article also explores the thermal stability and reliability of the two contact metals employed here.